A semiconductor test system tests various types of semiconductor devices. One of the semiconductor devices is a flash EEPROM (Electrically Erasable Programmable Read Only Memory) that is a semiconductor IC memory. Further, in a semiconductor test system, in order to improve cost performance and test efficiency, a simultaneous test is frequently used in which a plurality of semiconductor devices are tested at the same time.
In a flash EEPROM, a time length (the number of times) required for writing data therein differs due to the structure of the memory cells. Thus, one writing process may not complete the data storage in a memory cell. In this type or memory, a write process of several cycles (re-write process) are usually necessary, and based on that re-write process, the memory is tested as to whether the memory device as a whole functions correctly or not. In other word, only a first write process will not necessarily be enough to evaluate the quality of the memory under test. Thus, after each of the write processes, the memory device is tested and if the device is determined acceptable, the test is continued for the remaining memory devices by repeatedly writing the data therein. The number of times for writing the data in the memory is predetermined based on the specification of the memory devices.
When testing a plurality of such re-write memory devices simultaneously by a semiconductor IC test system, the comparison result of each device is fed back to a control circuit for each channel corresponding to the device as a re-write inhibit signal so as to prevent excessive writing or erasing repetitions, which will improve reliability of the memory devices.
In the foregoing conventional technology, the memory devices are tested by performing the re-write process in an address by address manner to determine the pass/fail of the memory device.
In recent years, NAND type flash memories are newly introduced in the market as one of the flash memories. The NAND type flash memory can be re-written and evaluated as to pass/fail as a unit of page or byte. Therefore, the NAND type flash memory is distinguished from the conventional NOR type flash memory which is re-written address by address as a unit of bit.
FIG. 2 shows an example of semiconductor test system known to the inventor which has a simultaneous test function for testing a plurality of semiconductor memory devices that can be re-written. As shown in FIG. 2, the output signal of the memory device under test is applied to a pass/fail judgement circuit 1. A fail detection signal from the pass/fail judgement circuit 1 is selected by a selector 2 to match the corresponding channel of the test system based on the structural conditions of the memory device under test. For instance, the fail signal is selected and output according to the bit structure of input and output of the devices, such as 4 bit, 8 bit, . . . 18 bit and the like.
The fail signal is latched by a flip-flop 3 with a timing of a clock signal 101 for each address of the memory device. A logical AND is performed for the fail signal and a reference clock MCLK1 by an AND gate 4. A high level is fixedly provided at the data input terminal of a flip-flop 5. The flip-flop 5 is triggered by the output signal of the AND gate 4 to save this fail information. In an AND gate 6, the output signal of the flip-flop 5 passes therethrough when a write prohibition mode is activated. A selector 7 selects a channel for which the re-write operation should be prohibited. The timing is then adjusted by a clock signal MCLK2 by a flip-flop 8 and is output from a re-write control circuit 100 as a prohibition signal 102.
When the simultaneous test is carried out, the re-write prohibition signals of the number equal to the number of the devices under test are required. Therefore, in addition to the re-write control circuit 100, a re-write control circuit 200 for a channel 2 and a re-write control circuit 300 for a channel n are also provided.
FIG. 4 is a flow chart showing a control operation to carry out the re-write procedure for each address of the memory device. As shown in FIG. 4, an initial value (N=1) defining the first number of re-write procedure is set (step 502) after the start (step 501) of the operation. Then, the program command is set, and a program write process is performed (step 504) for the memory device under test. A verification command is set in the next step, and a verification process is performed (step 506) for the output of the memory device under test. During this process, when the verification result is not "pass", the re-write operation will be repeated (step 507). Unless the number of re-write operation exceeds the upper limit (for example, 10 times), the setting routine (step 508) is carried out for setting the program command in the step 503. When the upper limit is reached in the step 508, the memory device under test is regarded as defective, and the test process ends as a fail end (step 510).
When the verification result shows "pass" in the step 507, it is determined whether the test execution address is the last address of the memory device under test (step 509). If the last address of the memory device is not reached, the next address is tested (step 512) by returning to the step 502, and the foregoing operation is repeated. If the last address is reached at the step 509, the operation procedure ends as a pass end (step 511).
As described in the foregoing, a time effective memory test can be performed for a memory device which is re-written in a address by address basis. However, the following problems arise when testing a memory device that operates per each page such as a NAND type flash memory in using the above noted semiconductor test system.
In the semiconductor test system of FIGS. 3 and 4, it is determined as to whether the re-write operation should be performed based on the pass/fail result for each address of the memory device. Hence, at the timing of the end of each page of the memory address, the test results for the addresses within the page are not remained. In other words, re-write the control operation with respect to each page of the memory cannot be attained.
In addition, in the example of FIGS. 3 and 4 in which the re-write operation has to be carried out on the address by address basis, the overall time required for the test has to be longer than required in testing the memory device per page of the address.
The purpose of the present invention is to eliminate all of the drawbacks in the foregoing. It is an object of the present invention to provide a semiconductor test system which is capable of performing a simultaneous test for testing a plurality of memory devices at the same time as well as carrying out the re-write operation in a page by page manner of the memory address, and as a result, reducing the overall test time.